Job Details

About the Role:

As the Hardware Lead, you will serve as the technical cornerstone driving the architecture and implementation of Reconceive's next-generation analog MAC IP and custom memory.

At Reconceive, we believe the future of AI compute relies on achieving unprecedented power and performance through architectural innovation and fundamental analog physics, rather than relying solely on brute-force digital node-scaling.

In this cross-functional leadership role, you will operate seamlessly across transistor-level circuit design, physical silicon characterization, and system-level architecture.

You will be responsible for the design of highly optimized custom hardware in established commercial CMOS technologies, as well as the development of robust automated pipelines that correlate empirical silicon telemetry with behavioral models for continuous, post-silicon optimization.

This role will interface closely with our AI team to co-develop model training capabilities and drive the adoption of AI-enabled automation across the design lifecycle.

Responsibilities:

• Mixed-Signal Hardware Architecture: Architect, model, and design Reconceive's analog MAC IP. Champion advanced Design-for-Manufacturing (DFM) practices to aggressively mitigate variation, mismatch, and parasitic challenges inherent to highly optimized mixed-signal compute.
• Custom Memory Leadership: Lead the end-to-end architecture, design, and layout optimization of custom, highly efficient SRAM tailored for low-power, high-throughput AI acceleration.
• Data Converter Design: Architect high-performance, ultra-low-power data converters (with a strong emphasis on SAR ADCs) and switched-capacitor circuits optimized for stringent system-level power and area constraints.
• Behavioral Modeling & Algorithmic Co-Design: Build and maintain high-fidelity behavioral models of the physical hardware. Provide critical feedback to the algorithm and systems teams to guide hardware-aware exploration.
• Post-Silicon Characterization & Calibration: Design robust physical characterization protocols. Develop automated data pipelines (Python/MATLAB) with support from our SW/AI team to correlate empirical silicon telemetry with behavioral models, ensuring highly accurate post-silicon predictability.
• Silicon Lifecycle Ownership: Perform rigorous feasibility studies to validate performance. Oversee third-party IP integration, chip bring-up, and system-level debugging.
• Mentorship & Organization Building: Guide layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior engineers and assist executive leadership with strategic hiring to scale the hardware organization.

Qualifications:

(Note: We recognize this is a highly multi-disciplinary role. We encourage applications from "T-shaped" engineering leaders who possess world-class depth in core areas—such as Custom Memory or Analog Design—paired with a strong aptitude and desire to master surrounding domains like Python automation and AI co-design.)

Minimum Qualifications:

• Education & Experience: MS or Ph.D. in Electrical Engineering (or equivalent) with 10+ years of proven, hands-on industry experience. Exceptional track record as a chip lead taking complex mixed-signal/analog designs to volume production.
• Foundational Analog Mastery: Deep, practical expertise in system and circuit design. Must demonstrate a first-principles mastery of device physics, variation mitigation, mismatch analysis, and rigorous DFM methodologies, with a proven track record of successful tape-outs in commercial CMOS processes.
• Custom SRAM (Mandatory): Extensive, demonstrable experience in the design, layout supervision, and silicon-proven implementation of custom, high-performance SRAM arrays.
• Data Converters: Deep expertise designing energy-efficient data converters (with a strong emphasis on SAR ADCs, though experience with algorithmic or pipelined topologies is highly valued) and switched-capacitor circuits.
• Data & Automation Proficiency: proficiency in Python and/or MATLAB. with demonstrated ability to build automated characterization pipelines that extract, process, and correlate physical silicon data with high-level system models.
• Analog & Digital Design: Extensive experience designing essential analog functions (filters, op-amps, bias circuits, oscillators) and high-speed/low-power custom digital logic.
• EDA Tool Mastery: Expert-level proficiency with industry-standard IC design and verification toolchains (e.g., Cadence Virtuoso, Siemens EDA / Calibre, SPICE/FastSPICE simulators).
• Startup DNA: Ability to thrive in a fast-paced, highly ambiguous environment; willing to roll up your sleeves, wear multiple hats, and execute with urgency while laying the groundwork for a scalable hardware team.
• Reliability: Strong foundational knowledge of ESD, EMIR, and device lifetime reliability problems and their practical design solutions.

Preferred Qualifications:

• Experience with variation-aware design and high-sigma yield analysis tools (e.g., Siemens Solido Variation Designer).
• Advanced behavioral modeling experience (e.g., Verilog-A / Verilog-AMS) for mixed-signal system verification.
• Direct exposure to machine learning platforms, neural network topologies, and hardware-aware training loops.