Job Details

Principal Substrate and Packaging Engineer

Fully onsite in the San Francisco Bay Area

Full time opportunity

$400-500K total compensation package- base, bonus, stock (depends on skillset/experience level)

Industry leader in semiconductor design focused on advanced IC packaging and high-speed interconnect technologies. In the role, you will have primarily be responsible for the layout, routing, and functionality of packages and substrates, including design of high-speed lines.

What You'll Do

• Design and layout advanced IC packages, substrates, and interposers, including high-speed signal routing
• Collaborate closely with electrical, mechanical, SI/PI, and program teams during front-end and detailed layout
• Define layout rules, panelization strategies, and stack-ups with substrate and package vendors
• Perform peer design reviews and contribute to layout best practices and flow improvements
• Execute DRC and LVS checks to ensure layout correctness
• Support post-fab evaluation, including visual inspection, electrical validation, and high-speed characterization
• Develop and apply script-based layout automation to improve efficiency and quality
• Simulate layouts and recommend design optimizations to meet performance and reliability targets

Required Background

• BS/MS/PhD in Electrical, Computer, Mechanical Engineering, or related field
• 10+ years of hands-on experience in IC substrate and package layout
• Deep expertise with EDA layout tools, such as: Calibre/Klayout, Cadence Allegro Package Designer, Innovus and Virtuoso
• Multilayer and high-speed layout
• RF design fundamentals
• Package/substrate manufacturing processes and materials
• Surface-mount technology (SMT)