Job Details

About the Role

A NauWork client is seeking an

ASIC Architect to join their team. The position is primarily based in the San Francisco Bay Area. This client is a high-growth, venture-backed semiconductor company building the next generation of infrastructure for large-scale AI workloads. They are focused on eliminating data center bottlenecks for training and inference of large AI models through novel innovations across chips, systems, and software. Led by a seasoned leadership team with a history of successful exits and category-defining products, the company offers the opportunity to work on first-of-its-kind technology with a direct line of sight to market impact. Their solutions are already being validated by leading cloud and hyperscale customers. As an ASIC Architect, this person will play a central role in defining and implementing industry-leading networking silicon for advanced AI data center deployments. This position will translate system and customer requirements into robust, scalable ASIC architectures that optimize throughput, latency, power, and area. The role will work cross-functionally with system architects, RTL, verification, firmware, and physical design teams, driving architectural decisions from concept through silicon bring-up and productization. This is an opportunity to shape the architecture of next-generation AI networking products at an early and influential stage.

Responsibilities

• Translate high-level system requirements and customer use cases into detailed ASIC architecture and functional specifications.
• Collaborate closely with chip and system microarchitects to align ASIC architecture with system-level performance, latency, and power goals.
• Guide modeling and feasibility analysis of packet flow behavior through the switch datapath, including throughput, latency, power, and area trade-offs.
• Work with RTL, Verification, Physical Design, and Firmware teams to ensure architecture is correctly implemented and efficiently handed off to downstream teams.
• Define and drive integration of internal and third-party IP (e.g., MAC, PCIe, SerDes) into the overall ASIC architecture, including interface and protocol requirements.
• Participate in and often lead architecture and design reviews, performance modeling efforts, verification strategy input, and architectural trade-off analysis.
• Contribute to post-silicon validation for both performance and functional correctness.
• Investigate and resolve complex issues in ASIC datapaths and packet-processing pipelines in close collaboration with hardware, firmware, and system engineering teams.
• Maintain clear and thorough documentation of architectural specifications, assumptions, and design decisions.

Qualifications

• MSEE (or closely related field) with 10+ years of experience in ASIC architecture and design, preferably in networking or high-performance data-path focused products.
• Strong background in networking ASIC or related high-performance compute/parallel processing architectures (e.g., complex memory crossbars, buffering schemes, scheduling algorithms, high-speed datapaths).
• Deep understanding of networking protocols such as Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc., or demonstrated ability and willingness to ramp quickly to expert level.
• Proven experience in microarchitecture definition, performance modeling, and architectural trade-off analysis.
• Ability to develop architecture-level behavioral models for performance and functional validation.
• Hands-on experience across the ASIC lifecycle, from concept and feasibility through design, tape-out, and productization.
• Familiarity with high-speed I/O integration (e.g., PCIe Gen5/Gen6, high-speed SerDes) and software control plane interface architectures.
• Solid understanding of how physical design constraints (timing, area, power, floorplanning) impact packet processing and buffering architectures.
• Strong analytical and problem-solving capabilities with a high level of attention to detail in debugging complex system and silicon issues.
• Excellent written and verbal communication skills, with the ability to document and explain complex architectural concepts to both technical and non-technical stakeholders.

Preferred Skills

• Direct experience architecting large-scale networking ASICs or switch/router silicon for data center or cloud environments.
• Background working on AI, HPC, or other latency-/bandwidth-sensitive workloads and understanding their implications for network and memory system design.
• Experience with modeling and simulation tools for architecture and performance analysis (e.g., SystemC, C/C++, Python-based simulators).
• Prior involvement in post-silicon validation, bring-up, and performance tuning of complex networking or compute SoCs.
• Experience collaborating with hyperscaler or cloud providers on silicon requirements and joint development programs.
• Track record of technical leadership, mentoring other engineers, and influencing product or roadmap decisions.

Equal Opportunity Statement

The company is committed to diversity and inclusivity in the workplace.