Job Details

Role Description

In this role, you will help create chip libraries, IP, and complete designs. You will utilize your expertise in DV to ensure quality and functionality throughout our product stack, working alongside a cross-functional team of world-class engineers and researchers.

We're looking for candidates who are passionate about pushing the boundaries of chip design, and excited to work at the intersection of semiconductors and AI.

Key Responsibilities

• Collaborate with ML and SW specialists as one of our verification domain experts
• Create testbenches, test plans, benchmarks
• Designing and operating novel automated design verification methodologies

Qualifications

• Bachelor's or Master's degrees in EE/CS
• 5-10 years of experience in Design Verification
• Proficiency in the SystemVerilog and UVM languages
• Experience with writing test-plans, test benches, and analyzing coverage metrics
• Excellent written and verbal communication skills
• U.S. Citizen, Permanent Resident, or valid work visa

Preferred Qualifications

• Python coding skills, for EDA automation and design parsing
• Proficient in the use of Git (branches, pull requests, merging, rebasing …)
• Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5 …)
• Experience with various verification approaches (SystemVerilog, UVM, CocoTB, Formal Verification …)
• Experience with FPGA development and/or debug (Vivado, Vitis, Quartus, ACE …)
• Comfortable working in a dynamic, research-heavy startup environment