Job Details

We are hiring a Senior RTL Design Engineer to own memory subsystems in high-performance AI accelerators. This role will deliver the bandwidth, latency, and power profile needed for large-scale compute.

What you'll do

• Architect and implement memory controllers for HBM2E/3, LPDDR5/6, and DDR5.
• Deliver RTL from spec to tape-out: coding, simulation, synthesis, optimization.
• Integrate memory PHY, interposer, and DRAM interfaces into SoC.
• Collaborate with architecture, verification, and PD teams to close timing and power.
• Debug across pre- and post-silicon phases; ensure first-pass success.
• Contribute to other subsystems as gaps arise.

Skills & background

• BS/MS in EE/CE, 8+ years of RTL design in advanced SoCs.
• Strong SystemVerilog coding and micro-architecture skills.
• Proven experience with HBM (2/3), LPDDR (5/6), DDR (4/5).
• Solid grasp of timing closure, CDC, power optimization.
• Familiar with synthesis, lint, and UVM/verification methodologies.

Mid-Senior level

Full-time

Engineering and Design

Industries: Semiconductor Manufacturing and Computers and Electronics Manufacturing

The base pay range for this position is $190,000.00/yr - $230,000.00/yr.