Job Details

About Architect
Architect is an AI research and product lab for chip design. We build AI models and systems that explore, design, optimize, and verify new hardware. Our mission is to reimagine chip design with AI-reducing ASIC design time and cost while enabling a new generation of ultra-efficient, domain-specific chips that will power the future of computation.
Born out of Stanford, our team blends researchers and engineers from DeepMind, Meta, Apple, Intel, and other frontier labs. Backed by leading VCs and angels, including the Chief Scientist at Google, Stanford professors, and founders of chip companies, Architect operates in stealth at the frontier of AI4EDA-building the intelligence layer for the hardware revolution.

The Role
As a Founding Member of the Technical Staff (ML) at Architect, you will be at the forefront of training AI models for chip design tasks such as RTL code generation, verification, architectural exploration, multimodal reasoning, and tool use.

This is a highly hands-on, 0→1 role where you will design multi-agent systems that reason, generate, and verify real silicon while integrating directly into chip engineers' workflows. You will work across the full ML lifecycle-data pipelines, training, deployment, iteration, and scaling-while collaborating closely with hardware and product teams. You will push the limits of LLMs, post-training, reinforcement learning, and graph-based methods for EDA.

What You'll Do

• Train and deploy ML systems for chip design tasks including RTL generation, verification, architecture search, and tool use
• Design and implement multi-agent systems for reasoning, generation, and verification of real silicon
• Own the full ML lifecycle from data curation and preparation through training, deployment, and iteration
• Build and productionize reinforcement learning and post-training pipelines
• Prototype, benchmark, and scale distributed ML training and inference systems
• Collaborate closely with hardware and product teams to integrate AI directly into chip design workflows
• Experiment at the frontier of LLMs, multimodal models, and structured code generation for EDA

• PhD in Computer Science, EECS, Mathematics, or a closely related field with a focus in ML/AI
• Or BS/MS with a strong research-engineering background from frontier labs or deep-tech AI startups

• Strong ML background with interest in applying AI to hardware design
• No prior chip design background required

• 2+ years of industry experience (4+ years preferred)
• Experience building end-to-end ML pipelines including data curation, model training, mid-training, and post-training using reinforcement learning

• Deep expertise in reinforcement learning and post-training workflows
• Proven experience taking models from research to real-world deployment
• Experience training and fine-tuning LLMs and code models for reasoning, tool use, and structured generation
• Hands-on experience with local LLM/VLM deployment (vLLM, sgLang, LM Studio, Ollama, etc.)
• Experience with distributed training and serving (QLoRA, ZeRO, PagedAttention, CUDA, PyTorch parallelism)
• Comfortable owning reward modeling, environment design, test-time optimization, and scaling
• Fast-moving builder mindset with tight feedback loops
• Strong focus on pushing state-of-the-art performance under real-world engineering constraints

• Comfort with cloud-native architectures and distributed systems

• Experience at post-training teams at OpenAI, Anthropic, DeepMind, Mistral, MSL, Cohere, or similar
• Foundation in Electrical/Computer Engineering or chip design/verification (not required)
• Publications at top ML or EDA venues (NeurIPS, ICLR, ICML, DAC, ICCAD, DVCon)
• Prior founding-team or early ML hire at an AI deep-tech startup

• Competitive salary and meaningful equity
• Fast-paced startup with high autonomy and visible impact
• Direct exposure to cutting-edge AI-driven chip design challenges