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Eximietas Design is or a talented SoC Design Engineer with strong hands‑on experience working on ARM Cortex‑M7–based subsystems. In this role, you'll be responsible for RTL micro‑architecture, integration, synthesis, and debug of M7 CPU complexes and AMBA interconnect components. You'll collaborate with internal and external IP teams to deliver high‑performance, low‑power SoC solutions for next‑generation embedded products.

This opportunity is ideal for engineers who are passionate about ARM-based SoC architecture and enjoy working across design, integration, and verification boundaries.

Key Responsibilities

• Design and integrate ARM Cortex‑M7–based subsystems within SoC environments.
• Develop micro‑architecture specifications, RTL code, and documentation for M7 CPU, bus interconnects, and peripherals.
• Implement and verify AMBA (AXI, AHB, APB) protocols and related SoC interfaces.
• Perform RTL quality checks — Lint, CDC, RDC — and ensure synthesis readiness.
• Collaborate with verification teams to establish UVM‑based co‑simulation environments using ARM CPU models.
• Participate in timing constraint development, synthesis, and timing closure.
• Support CoreSight debug infrastructure integration and system trace validation.
• Work closely with IP vendors and internal SoC integration teams to ensure seamless IP delivery and SoC bring‑up readiness.

Required Skills & Experience

• 10+ years of experience in SoC RTL design and integration, including ARM Cortex‑M7 subsystems.
• Strong understanding of ARM architecture and AMBA bus protocols (AXI/AHB/APB).
• Proficient in Verilog/SystemVerilog for RTL design and simulation.
• Experience with synthesis, STA, Lint, CDC, and debug tools (Spyglass, DC, PrimeTime, Verdi, etc.).
• Hands‑on experience working with CoreSight debug, memory interfaces (QSPI, UART, GPIO), and peripheral integration.
• Familiarity with UVM‑based verification environments and co‑simulation with ARM models.
• Strong analytical, debugging, and communication skills, with ability to collaborate across design and verification domains.

Preferred / Nice to Have

• Experience with DRAM memory controllers and interfaces (DDR3/DDR4/LPDDR).
• Exposure to FPGA prototyping or emulation platforms.
• Familiarity with low‑power design methodologies and UPF flow.
• Knowledge of ARM CoreLink NIC or interconnect fabric design.

Education

• Bachelor's or Master's degree in Electrical / Electronics / Computer Engineering or related field.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Engineering and Information Technology

Industries

Engineering Services and Semiconductor Manufacturing