Job Details

• Full chip and Block constraints development and constraints generation.
• Full chip and Block Synthesis, STA and timing closure using Primetime and DMSA flow

Run and debug Formality and VCLP Tools

• Interfacing with internal external teams including Design, IP, Library
• Methodology & Flow development of Synthesis, Formality, STA & Timing Closure

• Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements --