Job Details

Overview

Digital Design Engineer – AI/EDA Automation (Contract) role at Partcl.

Base pay range

$20.00/yr - $40.00/yr

What You Will Do

• Help us design and verify digital logic using ML-assisted EDA workflows.
• Work across RTL, SPICE, and PDK layers to push real blocks through both open-source and proprietary toolchains.
• Write and verify RTL (Verilog/SystemVerilog) with LLM-assisted automation.
• Run synthesis, simulation, and timing analysis in open and closed EDA flows.
• Simulate SPICE netlists and debug transistor-level behavior. Script automation in Python/C++ to connect design stages.

Requirements

• Strong RTL design and verification background.
• Familiar with SPICE simulation and PDK fundamentals.
• Experience with Yosys/OpenROAD or commercial EDA tools.
• Hands-on, fast-moving, results-focused.

Seniority level

• Entry level

Employment type

• Contract

Job function

• Engineering and Information Technology

Industries

• Technology, Information and Internet

Location: San Francisco, CA