Job Details

Overview

Senior SW Architect EM/IR and MORE - Bay Area, Worldwide #6982. My client is an international leader in the highly specialized EDA tools industry with a long history of successful EDA and varied tools covering major parts of the flow and integrating with all other major flows. This position is for a high-performing R&D engineer to lead their R&D team developing market-leading (to name a few) EMIR, DRC, Cell/Memory characterization, interconnect parasitic extraction tools and more. Your expertise will lead other engineers in innovating highly productive flows in these analog and digital flows.

Responsibilities

• Research, design, and development of innovative solutions to complex problems leading to highly differentiated and high-quality production software.
• Designing technical and product requirements specifications.
• Designing interfaces with third-party tools to build different flows which include (depending on product and experience) interconnect parasitic extraction or DRC/LVS, or EMIR or Cell/Memory Characterization.
• Closely work with PE and PV teams to define product requirements, roadmap and product validation strategies.
• Participate in product documentation process.
• Designing very efficient data structures and algorithms.
• Runtime and memory requirements optimization.
• Designing, developing, debugging and maintaining complex software written in C/C++, taking ownership of specific customers and tool integration issues, communicating status within R&D and to management.

Requirements

• MS/PhD in Mathematics/Physics, Computer Science or Electrical Engineering. Doctorate or equivalent industrial experience preferred.
• Deep understanding of one or more of the above techniques is a must, 5+ years EDA experience in one or more of the above tools or adjacent EDA areas on digital and analog flows.
• Extensive experience in software engineering, complex C/C++ software development, data structures/algorithms and parallel computing architecture.
• Good written and spoken English, Mandarin a plus

Preferred Experience

• Understanding of post-layout simulation flows, i.e. EMIR, STA etc
• Same or similar position in one of EDA companies.
• Experience with adjacent EDA areas/tools (LVS, post-layout simulation, etc).
• Desirous of starting new and innovative products

To learn more about this and other openings, contact Mark Gilbert anytime by email, ...@eda-careers.com or call 305-###-####x3. Please include your resume so we can have a more precise conversation.

Employment details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Engineering and Information Technology
• Industries: Software Development, Semiconductor Manufacturing, and Computers and Electronics Manufacturing