Job Details

Job Description:

Join our dynamic team and collaborate with cross-functional experts to implement cutting-edge designs in test access mechanisms, I/O BIST, memory BIST, and scan compression. In this role, you will:

• Collaborate with third-party IP vendors to integrate memory BIST, scan, PHY I/O BIST, and other DFT logic into a seamless streaming scan fabric with a sequential scan compressor/decompressor.
• Partner with DFT solutions vendors to:
• Port patterns at the top level.
• Implement memory BIST interfaces for high-performance processor IP.
• Develop high-speed I/O solutions for logic scan testing.
• Work closely with physical designers to validate DFT timing constraints, RTL designers to ensure test design rule adherence, and test engineers to bring patterns to life on automated test equipment (ATE).
• Drive the development and deployment of innovative DFT methodologies for our next-generation products.

Required Experience and Skills:

• Proficiency in scan and iJTAG.
• Master's degree in Electrical Engineering (MSEE) or equivalent experience.
• 7+ years of experience in DFT or related domains.
• Demonstrated expertise in defining scan test plans, BIST (including memories and I/Os), fault modeling, ATPG, and fault simulation.
• Strong analytical skills for verification and validation of test patterns and logic on complex, multi-million gate designs using vendor tools.
• Familiarity with cross-functional areas, including RTL and clock design, STA, place-and-route, and power considerations, ensuring balanced trade-offs.
• Hands-on experience in silicon debugging and bring-up on ATE, with an understanding of pattern formats, failure processing, and test program development.
• Strong programming and scripting skills in languages such as Perl, Python, or Tcl.